Recently, there is an increasing number of devices taking the form of a multi-core processor, which is a computer having plural processor cores, rather than the form of a single-core processor, which is the computer with one processor core mounted thereon. In the case of applying a conventional software asset for the single core to the multi-core processor, since one program is executed by plural cores, inheritance of resister values must be taken into consideration.
For example, with respect to technologies regarding generation of an executable object, a technology has been disclosed of implementing a register as a temporary register on an assembler program and judging the live range of the temporary register by flow analysis, replacing the temporary register with an actual register, at the assembly stage (see, e.g., Japanese Laid-Open Patent Publication No, H8-234997). The technology according to Japanese Laid-Open Patent Publication No. H8-234997 can clarify the live range of the register. This technology, therefore, makes it possible to avoid an unnecessary insertion of synchronization processing or a missed insertion of the synchronization processing in the case of changing assembler code written for the single core to be will processed in parallel by the multi-core processor system.
With respect to technologies regarding load distribution within a multi-core processor system, for example, a technology has been disclosed of providing processing modules with profile information and determining the processing module to be executed by each core based on the profile information (see, e.g., Japanese Laid-Open Patent Publication No. 2006-99156). With respect to hardware technologies for parallel processing in a multi-core processor system, a technology has been disclosed that enables easy data transfer by having a 2-port register accessible by plural cores (see, e.g., Japanese Laid-Open Patent Publication No. H01-048163).
With respect to a method of synchronizing registers of the multi-core processor system, there is the technology using the cache coherency mechanism (hereinafter referred to as “conventional technology 1”). For example, in the case of synchronizing the register of a given core and the register of another core, firstly, the given core writes the value of the register to a cache memory. The cache coherency mechanism, upon detecting the writing of the register value into the cache memory, notifies the cache memory of the other core of the register value. Lastly, the other core reads in the register value from the cache memory of the given core and writes the value to the register of the other core. A sequence of operations described above makes it possible to synchronize the registers.
With respect to the method of synchronizing registers of the multi-core processor system, for example, a technology has been disclosed of preparing a specialized instruction to perform the synchronization (see, Japanese Laid-Open Patent Publication No. H04-195664). With the technology according to Japanese Laid-Open Patent Publication No. H04-195664, when a given core has executed the specialized instruction, the given core transmits the register value to another core and enters a suspended state until the other core executes a register transfer instruction, enabling processing equivalent to that of the conventional technology 1 to be executed by software, in one step.
FIG. 13 is an explanatory diagram of a register synchronizing method at the time of execution of a C program or a C++ program in the multi-core processor system of a conventional example. At the time of design, a compiler reads in a C/C++ source 1301 as a C source or a C++ source and generates a block 1302 and a block 1303 as a part of the executable object having synchronization control code added thereto. Portions corresponding to the synchronization control code are a block 1304 and a block 1305. For example, the C/C++ source 1301 includes two statements of “A=A+1;func(A);” and the block 1302 and the block 1303 are the executable objects corresponding to the two statements.
In the example of FIG. 13, even if the block 1302 and the block 1303 are executed by different CPUs, the blocks 1304 and 1305 make it possible to synchronize a register Gr1, enabling proper operation. For example, the block 1304 stores the value of register Gr1 to 0x0000FF00 designating an area of the cache memory, etc. Then, the block 1305 reads in the value stored at 0x0000FF00 and sets the value to the register Gr1. Thus, an executable object for a multi-core processor can be generated from a program for a single core by adding synchronization control code at the time of compiling (hereinafter referred to as “conventional technology 2”).
Among the technologies described above, however, the conventional technology 1, the conventional technology 2, and the technology according to Japanese Laid-Open Patent Publication No. H04-195664 newly add the synchronization control code. Therefore, when the conventional technology 1, the conventional technology 2, and the technology according to Japanese Laid-Open Patent Publication No. H04-195664 are applied to the assembler source, there has been a problem that the executable code is changed to the executable object to be generated. The assembler source is generated by a designer, for example, when he desires to reduce the number of instructions even by one step. Therefore, the assembler source is expected to be converted to machine language one to one and a careless addition of the executable code has given rise to, a problem that the volume of code quantity becomes greater than that intended by the designer.